1. Field of the Invention
This invention relates to a semiconductor switching device having multiple PN junctions, an insulated gate, along with a distinctive doping geometry and surface geometry. This invention also relates to a method of making such a device. More specifically this invention relates to an insulated gate bipolar transistor (IGBT) having a unique subsurface enhancement doping, a surface recess that accesses the subsurface doping, and a cathode contact in the recess.
2. Description of the Prior Art
An insulated gate bipolar transistor (IGBT) is an attractive semiconductor switching device because it provides relatively low forward conduction resistance. On the other hand, we have recognized that the current typical structure for an IGBT has a disadvantage in that it inherently contains a parasitic thyristor structure. For example, if the IGBT works by way of a PNP transistor, it will inherently have a parasitic NPN transistor that is cross coupled to the PNP transistor, to form a parasitic PNPN thyristor structure.
In the current typical IGBT of the PNP type, the PNP bipolar transistor is formed by a P+ anode layer, on which is disposed an N-type drift region. The doping in the n-type drift region varies over its thickness. A P-well is disposed in the N-type drift region, to complete the PNP structure. When the current typical IGBT is turned "on", conduction in the forward state utilizes the bipolar action of the above-mentioned PNP transistor to achieve a low forward voltage drop. During forward conduction, holes are injected from the P+ anode layer into the N-type drift region. These holes are collected by the P-well in the drift region.
In such an IGBT construction, an N-type annular "source" region is concentrically disposed within the P-well. A spacing between the outer peripheries of the "source" region and the P-well provides a circumferential "channel" region on the surface of the P-well inside its outer edge. An insulated gate control electrode is disposed on the "channel" region. A cathode contact for the IGBT makes a low resistance connection to both the annular N-type "source" region and the P-well portion exposed in the center of the annular N-type "source" region. This type of contact is also referred to herein as a "shorted" contact.
Voltage applied to the insulated gate electrode creates a low resistance electric path across the "channel" region of the P-well. This creates a low electrical resistance path between the N-type "source" region and the N-type drift region. This allows electron current to flow between them. This flow of electron current serves as a source of "base" current to the PNP transistor of the IGBT. Flow of "base" current to the PNP transistor, of course, controls flow of hole current between the P-type anode layer and the P-well. In summary, the flow of "base" current, and also the flow of hole current between anode and cathode, is controlled by the application of voltage to the insulated gate electrode over the "channel" region. Hence, turn-on and turn-off of the IGBT is controlled by application of voltage to the insulated gate electrode.
In the current, typical IGBT, the P+ anode region, the N-type drift region and the P-well form the PNP structure. Unfortunately, the N-type "source" region, P-well, and N-type drift region form a parasitic (unwanted) NPN transistor that is cross coupled with the PNP transistor. This forms the parasitic PNPN thyristor structure. The parasitic NPN transistor structure interferes with turn-off of the IGBT. The reason for this is that if the parasitic NPN transistor is turned-on, it is in parallel with the "channel" region and thus, provides an alternate source of electron current. As indicated above, the electron current through the "channel" region is used to control current through the IGBT. The parasitic NPN transistor subverts this control by obviating the need for the channel region as a source of electron current.
The annular N-type "source" region forms an annular pinch resistance area in the P-well. It is located between the bottom of the annular N-type region and the adjacent bottom portions of the P-well. The pinch resistance affects hole current entering the sides and outer bottom portions of the P-well. Hole current collected at those side and bottom portions of the P-well region must flow through the pinch resistance to get to the surface of the P-well in the center of the N-type annulus, where the cathode terminal is located.
The flow of hole current through the pinch resistance causes a voltage drop from the cathode contact to the outer portions of the P-well. The voltage drop across the pinch resistance can turn-on the inherent PNPN thyristor referred to above. The PNPN thyristor is turned "on" when there is a voltage drop exceeding about 0.7 volts between the outer periphery of the P-well and the annular N-type "source" region. The reason for this is that the annular N-type region is shorted to the central part of the P-well. Hence, they are at about the same potential. It is to be noted that the P-well/"source" region diode (i.e., PN junction) acts as an emitter/base junction for the parasitic NPN transistor mentioned above. If the voltage drop between the outer and inner periphery of the P-well exceeds about 0.7 volts, this emitter/base junction becomes forward biased and the parasitic NPN transistor turns "on".
As mentioned, the parasitic NPN transistor is cross coupled with the PNP transistor. Once turned "on", the NPN transistor provides a source of base current for the PNP transistor in parallel with that supplied by the insulated gate electrode. Unfortunately, the NPN source of current is not controlled by the gate electrode. This type of condition is referred to as latch up. When this occurs, gate control is lost and IGBT device damage is likely to occur. Therefore, it is of utmost importance to prevent latch-up from occurring during the normal operation of an IGBT.
In order to make an IGBT immune to latch-up, it is necessary to minimize the IR drop across the pinched portion of the P-well. This has been provided in the prior art by more highly doping the P-well. The doping is controlled by the P-well ion implant and drive-in. However, the amount of dopant, i.e., dose, of the P-well ion implant also controls the threshold voltage of the gate control electrode for the IGBT. Because reasonably low threshold voltages are generally required, the dose of the P-well cannot simply be increased to improve the immunity to latch-up.
To suppress latch-up, it is important to provide a low electrical resistance path between the pinch resistance area of the P-well and the cathode. This would include providing reduced contact resistance between the metallization forming the cathode contact and the P-well. Both aspects have been addressed in the past by providing a P+ deep diffusion, or "sinker" diffusion in the center of the annular N-type "source" region. This is shown in FIG. 1, which will hereinafter be more fully described.
The "sinker" diffusion, provides a good ohmic contact to the cathode metallization and a low resistance path from the metallization to the backside of the pinched P-well region. The "sinker" diffusion can also increase the amount of dopant in the pinched P-well region, which lowers its resistance.
One of the more important problems with the P+ sinker is that its alignment to the edge of the polycrystalline silicon gate is critical, and so is control of the diffusion process. It is important to recognize that when a dopant diffuses vertically, it also diffuses horizontally a substantially similar amount. If one tries to diffuse too deeply, a lateral diffusion problem can result. The P+ sinker can diffuse laterally into the "channel" region, and thus increase the threshold voltage of the IGBT. If the P+ sinker diffusion does not go deeply enough, it may not lower pinch resistance much or at all. Diffusion control and masking registration are critical here.
A further drawback, to the "sinker" diffusion solution for suppressing thyristor action, is that the N+ diffusion must be must be masked at the center of the cell to produce the N-type "source" diffusion annulus. The center of the cell has to be masked again to produce the cathode metallization, which contacts both the P+ sinker and the n-type annular "source" region but not the outwardly concentric gate electrode. Accordingly, the masks for the N-type annular "source" region limit the minimum size of the emitter opening. The reason is that it must have sufficient overlap with the source contact, including allowances for mis-registration between masks and critical-dimension variation. In order to allow for annulus contact tolerances, a wider n-type annulus has to be used. Providing the wider annulus is objectionable because it increases the overall size of the device, which is objectionable from several standpoints.